1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a bipolar transistor and a method of manufacturing the same.
2. Description of the Prior Art
FIG. 1 is a sectional view showing a bipolar transistor according to the first prior art. Referring to FIG. 1, reference numeral 1 denotes a p-type semiconductor substrate; 2, an n-type buried layer; 3, a p-type buried layer 3; 4, an n-type epitaxial layer; 5, a p-type well; 6, a field oxide film; 7, a p-type diffusion region; 8, a p-type base connecting region; 9, an insulating interlayer; 10, an n-type collector diffusion region; 11, an emitter electrode layer; 12, an n-type emitter region; 13, an insulating interlayer; 14, an insulating interlayer; 17b, a base wiring layer; 17c, a collector wiring layer; 17e, an emitter wiring layer; 101, an emitter electrode layer contact hole; 102b, a base contact hole; 102c, a collector contact hole; 102e, an emitter contact hole; and 201, an oxide film.
The bipolar transistor is arranged on the major surface of the p-type semiconductor substrate 1 and isolated from other elements by the p-type buried layer 3 and the p-type well 5. This bipolar transistor is constituted by an npn transistor having a vertical structure obtained by sequentially, vertically arranging the active regions of an n-type collector region, a p-type base region, and an n-type emitter region upward from the major surface of the p-type semiconductor substrate 1.
The n-type collector region is constituted by the n-type collector diffusion region 10, the n-type epitaxial layer 4, and the n-type buried layer 2. The p-type base region is constituted by the p-type diffusion region 7 serving as an intrinsic base region and the p-type base connecting region 8 externally connecting to a base. The n-type emitter region 12 is formed by diffusing an n-type impurity to the major surface portion of the p-type diffusion region 7 serving as the intrinsic base region. The emitter electrode layer contact hole 101 is formed by removing the insulating interlayer 9 on the n-type emitter region 12, and the emitter electrode layer 11 is formed in the emitter electrode layer contact hole 101. The emitter electrode layer 11 is constituted by, e.g., a polysilicon layer, and an n-type impurity is doped in the emitter electrode layer 11.
The base contact hole 102b is formed by removing the oxide film 201 and the insulating interlayers 9, 13, and 14 on the p-type base connecting region 8, and the base wiring layer 17b is formed in the base contact hole 102b. The emitter contact hole 102e is formed by removing the insulating interlayers 13 and 14 on the emitter electrode layer 11, and the emitter wiring layer 17e is formed in the emitter contact hole 102e. In addition, the collector contact hole 102c is formed by removing the oxide film 201 and the insulating interlayers 9, 13, and 14 on the n-type collector diffusion region 10, and the collector wiring layer 17c is formed in the collector contact hole 102c. The base wiring layer 17b, the emitter wiring layer 17e, and the collector wiring layer 17c consist of, e.g., an aluminum alloy.
The steps of manufacturing the bipolar transistor shown in FIG. 1 will be described below with reference to FIGS. 2 to 5.
As shown in FIG. 2, an n-type impurity is doped in the bipolar transistor formation region of the major surface portion of the p-type semiconductor substrate 1, and a p-type impurity is doped in the isolation region of the major surface portion of the p-type semiconductor substrate 1. The n-type epitaxial layer 4 is grown on the entire surface on the major surface of the p-type semiconductor substrate 1. In the same process as this growth process, the n-type buried layer 2 is formed by the n-type impurity doped in the bipolar transistor formation region of the major surface portion of the p-type semiconductor substrate 1, and the p-type buried layer 3 is formed by the p-type impurity doped in the isolation region of the major surface portion of the p-type semiconductor substrate 1.
A p-type impurity such as boron is doped in a portion of the n-type epitaxial layer 4 on the p-type buried layer by ion implantation or the like to form the p-type well 5. The oxide film 201 is formed on the entire major surfaces of the n-type epitaxial layer 4 and the p-type well 5, and a nitride film 202 is formed on the entire surface of the oxide film 201. The nitride film 202 is selectively left in the base, collector, emitter formation regions of the bipolar transistor by a photolithographic technique.
FIG. 3 shows the step following the step in FIG. 2.
Subsequently, the major surface of the n-type epitaxial layer 4 is thermally oxidized using the nitride film 202 as an anti-oxidant mask to form the field oxide film 6. Thereafter, the nitride film 202 is removed.
Phosphorus is ion-implanted in the resultant structure at an acceleration energy of 70 keV and a dose of 1.times.10.sup.16 cm.sup.-2 using, e.g., a photoresist film as a mask to dope an n-type impurity in the collector formation region of the bipolar transistor in the n-type epitaxial layer 4, thereby forming the n-type collector diffusion region 10 for extracting a collector potential. Thereafter, the resultant structure is annealed in a nitrogen atmosphere at 950.degree. C. for 30 minutes to activate the n-type collector diffusion region 10 and to diffuse the n-type impurity to cause the n-type collector diffusion region 10 to reach the n-type buried layer 2.
FIG. 4 shows the step following the step shown in FIG. 3.
Subsequently, boron is ion-implanted in the resultant structure at an acceleration energy of 20 keV and a dose of 5.times.10.sup.13 cm.sup.-2 using, e.g., a photoresist as a mask to dope a p-type impurity in the emitter formation region of the bipolar transistor in the n-type epitaxial layer 4, thereby forming the p-type diffusion region 7 serving as an intrinsic base region. This p-type diffusion region 7 is formed to have a junction depth of, e.g., about 150 to 200 nm.
Next, BF.sub.2 is ion-implanted in the resultant structure at an acceleration energy of 70 keV and a dose of 5.times.10.sup.15 cm.sup.-2 using, e.g., a photoresist as a mask to dope a p-type impurity in the base formation region of the bipolar transistor in the n-type epitaxial layer 4, thereby forming the p-type base connecting region 8. The resultant structure is annealed at 900.degree. C. for 20 minutes to recover damage occurring in the above ion implantation and activate the doped p-type impurity.
FIG. 5 shows the step following the step shown in FIG. 4.
Subsequently, the insulating interlayer 9 is formed on the entire surfaces of the oxide film 201 and the field oxide film 6. This insulating interlayer 9 is constituted by an oxide film deposited by, e.g., a CVD method. The insulating interlayer 9 and the oxide film 201 in the emitter formation region of the bipolar transistor are etched by a photolithographic technique to form the emitter electrode layer contact hole 101. This etching is performed by anisotropic etching such as RIE.
A polysilicon film having a thickness of about 200 nm is deposited on the insulating interlayer 9 and in the emitter electrode layer contact hole 101 by, e.g., a CVD method. The deposited polysilicon film is patterned using a photolithographic technique, and the remaining polysilicon film is used as the emitter electrode layer 11.
Next, for example, arsenic is ion-implanted in the resultant structure at an acceleration energy of 70 keV and a dose of 1.times.10.sup.16 cm.sup.-2 to dope an n-type impurity in the emitter electrode layer 11. Thereafter, the resultant structure is annealed in, e.g., a nitrogen atmosphere at 900.degree. C. for 20 minutes to diffuse the n-type impurity doped in the emitter electrode layer 11 to the major surface portion of the p-type diffusion region 7, thereby forming the n-type emitter region 12.
Subsequently, as shown in FIG. 1, the insulating interlayers 13 and 14 are formed on the entire surfaces of the insulating interlayer 9 and the emitter electrode layer 11. The insulating interlayers 13 and 14 are formed as a film having a two-layered structure obtained by sequentially stacking, e.g., an oxide film and a BPSG (borophosphosilicate glass) film.
In the base formation region of the bipolar transistor, the insulating interlayer 14, the insulating interlayer 13, the insulating interlayer 9, and the oxide film 201 are etched using a photolithographic technique to form the base contact hole 102b. In the emitter formation region of the bipolar transistor, the insulating interlayer 14 and the insulating interlayer 13 are etched using a photolithographic technique to form the emitter contact hole 102e. In addition, in the collector formation region of the bipolar transistor, the insulating interlayer 14, the insulating interlayer 13, the insulating interlayer 9, and the insulating interlayer 201 are etched using a photolithographic technique to form a collector contact hole 102c.
An aluminum alloy is deposited in the base contact hole 102b, the emitter contact hole 102e, and the collector contact hole 102c by, e.g., a sputtering method to form the base wiring layer 17b, the emitter wiring layer 17e, and the collector wiring layer 17c.
The collector electrode of the bipolar transistor obtained by the manufacturing method of the first prior art described above can be set to be 100 .OMEGA. or less because the n-type collector diffusion region 10 for extracting a collector potential is formed.
In addition, as a method of positively decreasing a collector resistance, as disclosed in Japanese Unexamined Patent Publication Nos. Hei 3-49256 and Hei 4-269835, methods of forming a groove in the collector formation region of a bipolar transistor and burying the groove with a polysilicon film are proposed.
The semiconductor device disclosed in Japanese Unexamined Patent Publication No. Hei 3-49256 is a BiCMOS device, having a bipolar transistor and a CMOS mounted on the same chip, in which the collector resistance of the bipolar transistor is reduced while the BiCMOS device is kept small in size. As the second prior art, this device will be described below.
FIG. 6 is a sectional view for explaining the structure of the semiconductor device disclosed in Japanese Unexamined Patent Publication No. Hei 3-49256 as the second embodiment and the steps in manufacturing the semiconductor device.
Referring to FIG. 6, reference numeral 91 denotes a p-type silicon substrate; 92a and 92b, n-type impurity diffusion layers; 93, a p-type epitaxial layer; 94, an n-type well; 95, a gate electrode of a CMOS portion; 96, a source/drain of the p-channel transistor of the CMOS portion; 97, a source/drain of the n-channel transistor of the CMOS portion; 98, the emitter portion of a bipolar transistor; 99, the base portion of the bipolar transistor; 910, the collector portion of the bipolar transistor; 915, an insulating interlayer; 921, a collector groove; and 922, an n-type impurity diffusion layer.
FIG. 7 shows the step following the step shown in FIG. 6.
The same reference numerals as in FIG. 6 denote the same parts in FIG. 7. Referring to FIG. 7, reference numeral 911 denotes a polysilicon layer.
FIG. 8 shows the step following the step shown in FIG. 7.
The same reference numerals as in FIG. 6 denote the same parts in FIG. 8. In FIG. 8, reference numerals 96a, 97a, 98a, 99a, and 910a denote contact holes, respectively.
A method of manufacturing the semiconductor device disclosed in Japanese Unexamined Patent Publication No. Hei 3-49256 will be described below with reference to FIGS. 6, 7 and 8.
As shown in FIG. 6, the collector groove 921 reaching the n-type impurity diffusion layer 92a is formed in the collector portion 910 of the bipolar transistor by the well-known photoetching method, an n-type impurity (e.g., phosphorus) is diffused to the side surface portion and bottom surface portion of the collector groove 921 by a thermal diffusion method to form the n-type impurity diffusion layer 922. Thereafter, the resultant structure is annealed at a temperature of 900.degree. to 1,000.degree. C. to anneal the insulating interlayer 915 consisting of PSG (phosphosilicate glass) and activate the n-type impurity diffusion layer 922.
As shown in FIG. 7, polysilicon is deposited by a CVD method to form the polysilicon layer 911. As shown in FIG. 8, the entire surface of the polysilicon layer 911 is etched to leave only the polysilicon layer 911 deposited in the collector groove 921 and to form the CMOS contact holes 96a and 97a and the emitter and base contact holes 98a and 99a of the bipolar transistor.
In the second prior art, according to the above manufacturing method, the collector portion 910 of the bipolar transistor is constituted by the collector groove 921 extending from the surface of the n-type epitaxial layer 94 to the n-type impurity diffusion layer 92a, the n-type impurity diffusion layer 922 formed along the side and bottom surface portions of the collector groove 921, and the polysilicon layer 911 buried in the collector groove 921.
As described above, according to the first prior art, the collector resistance of the bipolar transistor can be generally set to be 100 .OMEGA. or less because the n-type collector diffusion region 10 for extracting a collector potential is formed. However, as is apparent from the above manufacturing steps, the step of forming a photomask, and the step of implanting ions are required to form the n-type collector diffusion region 10. Therefore, in order to reduce the number of steps in manufacturing a bipolar transistor, as shown in FIG. 9, the step of forming the n-type collector diffusion region 10 is omitted, and the collector structure having no n-type collector diffusion region 10 is formed. In this case, however, the collector resistance becomes 100 .OMEGA. or more to be easily saturated, or other transistor characteristics are degraded. Reference numerals as in FIG. 1 denote the same parts in FIG. 9.
In the second prior art described above, the step of forming a photomask for forming the collector groove 921, the step of burying the polysilicon layer 911 in the collector groove 921, and the like are required, thereby increasing the number of manufacturing steps. In addition, since the step of forming the contact hole (collector groove) 921 in the collector portion 910 and the step of respectively forming the contact hole 98a and the contact hole 99a in the emitter and base portions must be performed as separate steps, the number of manufacturing steps cannot be reduced.